This invention relates to clock drivers, and more particularly for methods for differential clock driver circuits with skew tolerance.
Many complex digital systems rely on clocks to maintain timing boundaries and proper synchronization. Since clock lines are often long and may lead to many input, loading on clock lines is high. High-current clock drivers are needed to drive such large capacitive loads of a clock line.
Very high-speed systems sometimes use differential logic, where both a true and a complement signal are used for each input or output. External signal lines are often differential, such as when a twisted-pair cable is driven with both true and complement signals. Sometimes differential signals are used internally within a semiconductor integrated circuit (IC) chip, especially for clock lines since true and complement clock signals are needed by many logic blocks such as flip-flops and transmission gates.
Differential clock signals can be generated from a single clock input. FIG. 1 shows a prior-art differential clock driver that has a single-ended input. A single clock ICLK is input to inverters 10, 14. Inverter 10 drives the complement clock line, CLKB, while the true clock line CLK is driven by inverter 12.
A two-inversion delay (inverters 14, 12) occurs between ICLK and CLK, while only a one-inversion delay occurs to CLKB, caused by inverter 10. This can result in a timing difference or skew between CLK and CLKB. Such skews are undesirable. Since CLK and CLKB drivers may be located at different places on the layout of a chip, there is also skew problem due to process variation and layout routing. Thus even when input clocks are perfectly matched, some skew occurs.
FIGS. 2A-C are waveforms highlighting differential clock skews. FIG. 2A shows an input clock ICLK used to generate a differential clock. Ideally, the true and complement clock are exact inverses of each other with zero timing skew, as shown in FIG. 2B. The CLK and CLKB signals cross over at 1.25 volt, about half of the signal swing in the ideal case. The voltage at which the two signals have the same voltage at precisely the same time is known as voltage cross-over, or VOX.
The mis-match of delays in generating the true and complement clock signals introduces clock skew. FIG. 2C shows a more realistic case of differential clock skew. The CLK signal tends to have more delay than CLKB due to the additional inversion. Thus the CLK waveform is shifted to the right by a small amount relative to the CLKB waveform. The voltage cross-over occurs later than in the ideal case. The falling edge of CLK occurs late, so the VOX for the falling CLK edge is at a higher (earlier) voltage, such as 1.6 volts rather than 1.25 volts. For the rising edge of CLK, VOX is lower, since the falling edge of CLKB is faster than the rising edge of CLK. VOX for the rising edge of CLK is at 0.9 volt rather than 1.25 volts. Also, the rising edge of both clocks may be slower than the falling edges, which can also lower VOX for both cases.
Such skewed differential clocks may be used as input to more powerful clock drivers that are fully differential, having two (differential) clock inputs and two (differential) clock outputs. The final buffered differential clock can still have these clock skews even when fully differential clock drivers are used.
What is desired is a fully differential clock driver that is tolerant of clock skews on a differential clock input to the clock driver. A skew-reducing differential clock driver is desired.